Research Article
What if every component of a CPU was a trained neural network? Not approximately - exactly. nCPU proves this is possible, then goes further: a neural operating system, a GPU-native UNIX with compiled C, and structural immunity to timing side-channel attacks.
Neural networks are inherently continuous and approximate. Integer arithmetic is inherently discrete and exact. Prior work - Neural Turing Machines, NALU, Neural GPUs - achieved approximate results or worked on small bit-widths. nCPU closes this gap with a design principle called memorization-by-decomposition.
Break 32-bit ops into sub-problems with tiny input spaces
Train exhaustively on every possible input (8 entries, 65K entries)
sigmoid > 0.5 converts continuous activations to exact discrete bits
Wire sub-problems together structurally, like digital logic
Each mode represents a different point in the design space. The neural mode is the research contribution. The compute mode is the most powerful - it runs a complete UNIX OS and uses zero neural models.
Every ALU operation routed through trained PyTorch models. Zero arithmetic fallbacks.
| Operation | Model | Strategy | Latency |
|---|---|---|---|
| ADD / SUB / CMP | arithmetic.pt + carry_combine.pt | Kogge-Stone CLA (8 neural passes) | ~248 us |
| MUL | multiply.pt | Byte-pair LUT (65,536 entries) | ~21 us |
| AND / OR / XOR | logical.pt | Neural truth tables (28 params) | ~21 us |
| SHL / SHR | lsl.pt / lsr.pt | Attention-based bit routing (3 batched passes) | ~434 us |
| DIV | arithmetic.pt | Restoring division (32-bit loop) | Sequential |
| sin / cos / sqrt / exp / log / atan2 | 6 math models | Specialized neural approximators | 21–935 us |
Same GPU-resident architecture, but bypasses neural models for native PyTorch tensor arithmetic.
Same architecture, no neural overhead. Registers, flags, memory, and PC are still GPU-resident PyTorch tensors. The only difference: arithmetic uses torch.add(), torch.mul(), etc. instead of dispatching through .pt models.
Native Metal GPU compute shaders. Zero neural models. Compiled C runs directly on GPU silicon.
No neural models whatsoever. This is a qemu-style fetch-decode-execute loop written entirely in Metal Shading Language. 130+ ARM64 instructions including all data movement, arithmetic, logic, shifts, bit manipulation, conditionals, memory ops, branches, and system instructions. The entire UNIX OS - shell, filesystem, multi-process, C runtime - runs on this engine.
Neural mode is ~880x slower than compute - but it proves neural networks can do exact arithmetic. These are complementary findings, not competing approaches.
In conventional CPUs, multiplication is 3–10x slower than addition. In nCPU, the relationship is inverted: neural multiplication is 12x faster than neural addition.
Insight: Carry propagation, not operation semantics, is the dominant cost. Model size doesn't predict latency - the 4 MB multiply LUT (21 us) is 12x faster than the 38 KB adder (248 us).
Unlike typical ML systems evaluated on held-out test sets, nCPU's sub-components are verified by exhaustive enumeration of every possible input. This is a mathematical proof, not a statistical estimate.
| Model | Input Space | Verified | Result |
|---|---|---|---|
| Full adder (arithmetic.pt) | 2³ = 8 inputs | 8 / 8 | 100% correct |
| Carry-combine (carry_combine.pt) | 2⁴ = 16 inputs | 16 / 16 | 100% correct |
| Logical truth tables (logical.pt) | 5 ops × 4 = 20 inputs | 20 / 20 | 100% correct |
| Multiply LUT (multiply.pt) | 256 × 256 = 65,536 pairs | 65,536 / 65,536 | 100% correct |
Weights are frozen after training. Sigmoid outputs have margins > 0.4 from the 0.5 threshold. 100 repeated executions produce identical results. Accuracy is permanent by construction.
If the CPU can be neural, can the entire operating system? 17 modules, 11 trained models, zero fallbacks. All OS state lives as PyTorch tensors on GPU.
| Component | Neural Architecture | Accuracy |
|---|---|---|
| MMU | Embedding-based page table (VPN + ASID → PFN classification) | 100.0% |
| TLB | MLP eviction policy (5 features → score) | 99.6% |
| Cache Replacement | LSTM sequence model over access history | 99.7% |
| Prefetch | LSTM address predictor (next K page accesses) | 97.8% |
| Scheduler | Transformer encoder with self-attention over process queue | 99.2% |
| GIC (Interrupt Controller) | MLP priority encoder (96 floats → 32 scores) | 93.7% |
| Block Allocator | MLP region scorer for fragmentation minimization | 98.4% |
| Assembler Tokenizer | Character-level CNN (char → token type) | 99.4% |
| Assembler Codegen | MLP → 32 sigmoid bits (byte-identical to classical) | 100.0% |
| Compiler Optimizer | MLP peephole window classifier (3-instruction windows) | 95.2% |
| Watchdog | LSTM anomaly detector (8 metrics, ring buffer) | 100.0% |
Online adaptation: TLB, cache, and scheduler take single gradient steps during normal operation, adapting to workload-specific patterns in real time. No conventional OS learns from its own scheduling and caching decisions at runtime.
A complete UNIX environment running as compiled C on the Metal compute kernel. No neural models - pure GPU compute shaders executing real ARM64 binaries.
|), background (&), chaining (; && ||), redirect (> >>)fork/wait/pipe/dup2 via memory swapping (classic UNIX technique). Up to 15 concurrent processes, 1 MB backing store each. Round-robin scheduler, per-process fd tables, pipe blocking with wakeup.
Header-only freestanding libc. malloc/free/calloc/realloc, printf with full format specifiers, fork/wait/pipe/dup2/getpid/kill, qsort, strtol, sscanf, string functions.
| Operation | GPU Cycles | Notes |
|---|---|---|
| Fork + exit + wait | 216 cycles | Dominated by Metal dispatch overhead |
| Context switch | 166 cycles/switch | Memory swap + register save/restore |
| Pipe throughput (1KB) | 0.9 cycles/byte | Near-optimal utilization |
| Process create (N=8) | 62 cycles/process | Excellent scaling |
| Single vs multi IPS | ~3,030 IPS | 0% overhead for compute-only workloads |
All compiled from freestanding C with aarch64-elf-gcc -O2, executing on the Metal compute kernel. No neural models involved.
GPU-sandboxed execution provides structural immunity to timing attacks - without requiring constant-time coding, compiler annotations, or hardware mitigations.
AES-128 validated: Passes all 6 FIPS 197 test vectors on GPU. T-table timing attacks - the canonical AES side-channel vulnerability (Bernstein 2005) - are structurally impossible. No data cache, no cache lines, no cache-miss penalty. Every S-box lookup = exactly 1 cycle.
Bit-serial full adder, byte-pair multiplication LUT, neural truth tables for logic. Proved 100% exact integer arithmetic via memorization-by-decomposition.
Kogge-Stone parallel-prefix CLA reduced addition from 826us to 248us (3.3x). Shift vectorization from 2,833us to 434us (6.5x). Five novel findings about neural computation.
17 modules across 10 phases. Neural MMU, TLB, scheduler, cache, assembler, compiler. All neural, zero fallbacks. Online adaptation for TLB/cache/scheduler.
130+ ARM64 instructions in ~1,600 lines Metal Shading Language. C-to-GPU compilation pipeline. 42K–61K IPS sustained, ~4.4M IPS on nCPU ISA. Zero neural models.
25-command shell, freestanding C libc, in-shell compilation, multi-process (fork/pipe/wait/dup2). 13+ demo apps: crypto, games, VMs, HTTP server, MNIST. All on compute kernel.
GPU timing determinism (σ=0.0). AES-128 passes all FIPS vectors. T-table attacks structurally impossible. Three-layer defense: deterministic execution, SVC trap, dispatch masking.
First fully neural operating system - every component from MMU to compiler is a neural network
GPU-native architecture with zero CPU-GPU synchronization for all OS state
Neural multiplication 12x faster than neural addition, inverting the conventional CPU hierarchy
Memorization-by-decomposition as a general principle for exact neural computation
Neural compiler with learned peephole optimization passes trained from a classical oracle
Online adaptation of OS policies (TLB, cache, scheduler) during normal runtime operation
Structural timing side-channel immunity for real cryptographic primitives (AES-128, SHA-256)
Train a monolithic network to compute all 32 carries simultaneously, reducing addition from O(log n) to O(1).
Backpropagate through program execution for gradient-based program synthesis - learning instruction sequences via gradient descent.
Retrain all models on 64-bit operands, eliminating the bridge narrowing from 64-bit to 32-bit.
ICML 2027 for neural computation findings. OSDI/SOSP for GPU-native OS architecture and neural scheduling.
This work is licensed under CC BY 4.0. Free to share and adapt with attribution.
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